Making sense of DHRUV64 indigenous microprocessor | Explained

The story so far: On December 15, the Ministry of Electronics and Information Technology (MEITY) announced the launch of DHRUV64, an indigenous microprocessor that it said would strengthen the national indigenous processor pipeline. Its purported applications span the breadth of consumer electronics to industrial automation.
What is DHRUV64?
The DHRUV64 chip is a fully indigenous microprocessor developed by the Centre for Development of Advanced Computing (C-DAC) under MEITY’s Microprocessor Development Programme.
The microprocessor is a general-purpose ‘brain’ for electronics — a 64-bit, dual-core processor that runs at 1 GHz. These specifications could mean the processor is fast enough to run operating systems while also being efficient enough for embedded deployment.
India is a major market for processors yet continues to depend on imported designs and supply chains. To this end the Indian government has pitched for a “homegrown processor technology”. Such processors sit at the base of everything from telecom networks to industrial control. So whoever controls their design, toolchain, and update pathways will also control security assumptions and resilience during export controls or supply shocks.
What do DHRUV64’s specs mean?
DHRUV64 is not a chip meant only for simple sensing or appliance logic. In general 64-bit designs are used when users want modern operating systems and contemporary software.
The specified performance is low compared to top-tier consumer standards. Today’s state-of-the-art smartphone and laptop processors tend to combine many more CPU cores with higher peak clock speeds. They also include specialised blocks like graphic processing units (GPUs), which can efficiently handle machine-learning workloads.
This said, a lot of contemporary computing in the modern economy doesn’t demand topline CPUs. These applications include base station subsystems in telecommunications, industrial controllers, routers, and many automotive modules. They prize reliability and better hardware-software integration.
At the same time, as the technology publication The Register wrote, “Those are fields in which established chipmakers already offer mature products, and accompanying software and hardware development ecosystems. Even the most patriotic Indian electronics manufacturer would surely find it hard to put the DHRUV64 at the top of their bill of materials shopping list. India therefore has plenty left to do if DHRUV64 is going to win customers.”
What processors is India working on?
According to MEITY, DHRUV64 is part of India’s ecosystem of processors, including SHAKTI from IIT-Madras, AJIT from IIT-Bombay, VIKRAM from the ISRO-Semiconductor Lab, and THEJAS64 from C-DAC (2025). The needs these processors address include strategic operations, control systems in factories, spaceflight systems, and industrial automation.
MEITY has also pitched DHRUV64 as a platform on which startups, academia, and industry can build and test products on, “without relying on foreign processors”, and can develop prototypes for new system architectures at lower cost. This is commendable because all processors everywhere, from the Intel Core series to the Espressif processors in DIY electronics, only succeed when they have an ecosystem around them.
What is DIR-V?
RISC-V (pronounced “risk five”) is a set of basic instructions that a processor understands. A processor is like a cook who can only make the dishes written down in a recipe book. This book is the instruction set: it lists commands like “add two numbers”, “move data from memory”, “compare two values”, “jump to another step in a program”, etc.
RISC-V is an open instruction set, which means its core rules are publicly available and anyone can design a chip that follows them without paying a licence fee for the instruction set itself. This is different from instruction sets that are controlled by a company and licensed to others. There the chip designers will need to purchase licenses, sign contracts, etc. This is why governments and research groups sometimes prefer RISC-V.
RISC-V is also modular: designers can start with a small, standard core, then add extra features like faster arithmetics or security features depending on what the chip is meant for. Put differently, different chips can speak the same base language while still being fine-tuned for different tasks.
DHRUV64 is tied to the Digital India RISC-V (DIR-V) programme, which aims to build a portfolio of RISC-V-based microprocessors for industry, military, and consumer technologies. THEJAS32 was the first India-designed chip DIR-V chip to be fabricated (in Malaysia) and THEJAS64 was the second, manufactured at SCL Mohali. DHRUV64 is the third on this list. However, MEITY hasn’t said where DHRUV64 was fabricated, which leaves doubts about the supply chain.
What else don’t we know about DHRUV64?
MEITY’s announcement of DHRUV64 is thin on the engineering information required to judge the chip’s readiness. There are five issues in particular.
First, the claim about the chip’s performance hasn’t been contextualised in measurable terms. The headline specs, i.e. 1 GHz, 64-bit, dual-core, are not accompanied by benchmarks, details of the memory subsystem (e.g. cache sizes and memory controller features), input/output capabilities, and the performance per watt. The MEITY statement also says the design includes “modern architectural features” and “enhanced multitasking capability” but doesn’t specify what they entail.
Second, the statement claims the processor’s “modern fabrication leverages technologies used for high-performance chips” but doesn’t specify the foundry, packaging, yields or reliability targets. Applications in the telecommunications and automotive sectors in particular require these details because they’re used to determine the chip’s lifecycle availability and failure rates.
Third, MEITY’s claim that the chip is “fully indigenous” is ambiguous. The note highlights RISC-V’s open architecture and “no licence costs”. However “indigenous” can also an indigenous instruction set, indigenous core microarchitecture, indigenous system-on-chip integration, indigenous toolchain, indigenous fabrication or indigenous ownership of critical IP blocks.
Fourth, the announcement doesn’t address questions relevant to an OEM, e.g. when developer boards will ship, which operating systems are supported, what security features and audit mechanisms the chip has, and whether the government plans to use them in anchor scenarios (i.e. where by using them it will reduce the risks associated with adoption).
Fifth, the development roadmap is not clear. The statement says C-DAC’s next indigenous chip will be ‘DHANUSH’ and ‘DHANUSH+’; they appear to currently be in the engineering or design stage. MEITY itself hasn’t said how these chips will improve on DHRUV64.
However, the MEITY statement indicated DHANUSH will be a 1.2-GHz quad-core processor and that DHANUSH+ will be a 2-GHz quad-core processor. One 2023 C-DAC document also reported that DHANUSH will have a process node – a figure denoting the transistors’ size – of 28 nm. The Register reported that that of DHANUSH+ would be 14 or 16 nm.
What comes next?
India has been focusing on schemes to widen talent and the scope for start-ups. The ‘Chips to Startup’ programme, with an outlay of ₹250 crore over five years; the Design Linked Incentive scheme; and the INUP-i2i initiative are intended to improve access to nanofabrication facilities and training. As of 2025, the India Semiconductor Mission has also approved 10 projects in six States with investment commitments of ₹1.6 lakh crore.
Against this backdrop, the government’s plan for DHRUV64 seems to be to move towards system-on-chip families, more reference designs, better software support, and sufficient manufacturing and testing capacity for domestic products. The end goal is for Indian consumers to choose an Indian chip without assuming unacceptable costs or risk.